FIG. 8 is a cross-sectional view schematically illustrating a conventional field effect transistor. The FET includes a semi-insulating compound semiconductor substrate 1, such as gallium arsenide (GaAs), having a surface and a active layer 2 disposed in the substrate 1 adjacent the surface. The active layer 2 is usually formed by ion implantation and has a relatively low dopant concentration compared to the dopant concentrations of a source region 4a and a drain region 4b formed in the substrate 1 at opposite ends of the active layer 2. The source region 4a and the drain region 4b are generally formed simultaneously by ion implantation and usually have the same dopant concentrations. A gate electrode 5 is disposed on the surface of the substrate 1 on the active layer 2 and forms a Schottky barrier with the active layer. Ohmic contacts to the drain region 4b and the source region 4a are made by electrodes 7 and 8, respectively.
For high quality performance, the dopant concentration in the source and drain regions 4a and 4b is made as high as possible. However, when those regions are formed by ion implantation in GaAs, the dopant concentration cannot exceed about 2.times.10.sup.18 cm.sup.-3, thereby limiting the desired reduction in the source resistance. In addition, when there are crystalline defects within the substrate 1 that occur naturally or in the ion implantation process, a leakage current that is not influenced by the signal applied to the gate electrode can flow between regions 4a and 4b. As the FET becomes smaller, the leakage current becomes more significant and causes increasing problems.
A field effect transistor having a structure intended to reduce the resistance of the source and to reduce leakage current is shown in a schematic cross-sectional view in FIG. 9 and was described in GaAs IC Symposium Technical Digest, pages 147-150, 1989. In FIG. 9 and all other figures of this application, the same elements are given the same reference numbers. In the structure of FIG. 9, the source and drain regions 4a and 4b are disposed on the active layer 2 on the surface of, and not within, the semi-insulating GaAs substrate 1. The gate electrode 5 is disposed between the source and drain regions on the surface of the substrate and separated from those regions by electrically insulating side wall films 9b and 9a, respectively.
FIGS. 10(a)-10(d) illustrate in cross-sectional views a process for manufacturing the FET of FIG. 9. As shown in FIG. 10(a), after the formation of the active layer 2 by ion implantation and the formation of the gate electrode 5, which may be a refractory metal silicide such as tungsten silicide (WSi.sub.x), by vapor deposition and photolithographic processing, an electrically insulating film 9', such as silicon dioxide (SiO.sub.2), is deposited on the surface of the substrate and the gate electrode 5. The electrically insulating film 9' is etched by reactive ion etching (RIE) so that the film is removed from the substrate except for the residual side wall films 9a and 9b that remain at the opposed side walls of the gate electrode 5.
Thereafter, as illustrated in FIG. 10(c), the source and drain regions 4a and 4b are epitaxially grown, for example, by metal organic chemical vapor deposition (MOCVD). MOCVD is a selective process and the relatively highly doped semiconductor film that forms regions 4a and 4b does not grow on the gate electrode or on the side wall films 9a and 9b. Because the maximum dopant concentration can be higher in an epitaxially grown film than in an ion implanted region, the source resistance of the FET of FIG. 9 can be lower than the source resistance of the FET of FIG. 8. The FET of FIG. 9 is completed by forming the metal electrodes 7 and 8, as shown in FIG. 10(d).
A number of problems are created by the process of FIGS. 10(a)-10(d). For example, in the RIE removal of electrically insulating film 9', the surface of the substrate 1 is subjected to a plasma that may cause contamination and roughness of the surface. That surface roughness adversely affects the crystallinity of the source and drain regions 4a and 4b that are subsequently epitaxially grown. The poor crystallinity increases the resistance of those regions and the rough surface results in crystalline defects at the interfaces between the regions and the active layer 2. Those interface defects also increase source resistance despite the relatively high doping of the source region, limiting the performance improvement that can be achieved with this structure and method.
FIGS. 11(a)-11(d) schematically illustrate in cross-sectional views another method of making the FET structure of FIG. 9 but without the electrically insulating side wall films 9a and 9b. Initially, as shown in FIG. 11(a), the active layer 2 and a high dopant concentration layer 4' are successively epitaxially grown on substrate 1. A photoresist film 11' (not shown) is deposited and an aperture is opened in the film, leaving resist mask 11j in place. Using the mask 11j, the central portion of the high dopant concentration film 4' is removed by etching, followed by removal of the mask 11j.
The remaining portions of the high dopant concentration layer 4' are source and drain regions 4a and 4b, as shown in FIG. 11(b). In order to form a gate electrode, a film 5' of the gate material is deposited on the active layer 2 between source and drain regions 4a and 4b as well as on those source and drain regions. A photoresist mask 11k having a width equal to the width of the gate electrode is formed by photolithographic patterning of a photoresist film 11" (not shown) on the gate metal film 5'. The mask 11k is substantially centered between the source and drain regions 4a and 4b.
As shown in FIG. 11(c), after etching of the gate metal film 5' to define the gate electrode 5, the resist pattern 11k is removed. The FET structure is completed by the formation of the drain and source electrodes 7 and 8.
In the manufacturing method of FIGS. 11(a)-11(d), a desirably high dopant concentration can be achieved in the source and drain regions 4a and 4b because the layer 4' is epitaxially grown rather than being formed by ion implantation. Crystalline defects at the interface between the active layer 2 and layer 4' are significantly lower than those in the process described with respect to FIGS. 10(a)-10(d) because the surface is not subjected to a plasma before growth of layer 4'. However, the formation of the gate electrode in the step illustrated in FIG. 11(b) is extremely difficult. The gate metal film 5' has a concavity between the source and drain regions 4a and 4b where the photoresist mask 11k is formed. Since the thickness t of the photo-resist film 11" from which the mask 11k is formed varies significantly with position between the source and drain regions, i.e., is not planar, it is very difficult to form the photoresist mask accurately in both position and width. Usually, the photoresist film 11" is exposed to monochromatic light before development to form mask 11k. As is well known, the use of monochromatic light with a thin film of variable thickness, like the photoresist film 11", can produce light interference, resulting in variations in the exposure of the photo-resist film with the thickness t. As a result, as shown in FIG. 12, the width l of the mask has a sinusoidal variation with the thickness of the photoresist film. In order to obtain a mask 11k of desired width l in a desired position on gate metal film 5', it is important that the thickness of the photoresist film 11" and the mask width be carefully coordinated. As a result, it is very difficult to control the process of FIGS. 11(a)-11(d) and to repeatedly produce FETs having the same characteristics using that process.